Processor system for delay and distortion of broadband signals in real time

Kurzfassung

A Spanish research group has developed a processor system for delay and distortion of broadband signals in real time enabling a great storage capacity and keeping a high speed access. The research group is looking for licensing the patent.

Details

The processor consisting of a circuit that digitizes an RF signal with a bandwidth of up to 15 MHz, sampling it with an analog digital converter which works with a sampling frequency of 33 MHz and 12-bit resolution, and inputting it into a high-capacity memory bank (3 M x 12 bit) formed by dynamic RAM memories that emulates memories like "FIFO” (First In First Out), enabling a storage capacity far greater than classical FIFO and keeping a high speed access (30 nsec).

For the generation of delay, samples from the A/D converter are stored in memory and are moved one position in each sampling clock cycle, so that the maximum delay solely depends on the amount of memory used, and maximum resolution is a sampling clock cycle. The duration of the delay is digitally controlled through a meter working with the same sampling clock and controlling the amount of samples stored in memory. The total delay depends on the amount of memory and on sampling clock frequency, so that with 3 M x 12 bit and 33 MHz sampling frequency, 100 ms of peak delay can be achieved.

The phase distortion is generated by varying the frequency of the clock that controls the regime of digital analog converter output. This clock is formed by a voltage controlled oscillator, which the RF signal is input, causing frequency variations that result in changes in the sampling regime output. Since the regime of data entry is constant (because the input clock frequency is fixed), the result is a phase distortion that appears in the output signal, being equivalent to the process that occurs in real systems. The percentage of distortion is regulated by adjusting the amplitude of the RF signal that is input to the output clock through a digital attenuator.

The amplitude distortion is generated in the FIFO memories block output, through a kind of memory RAM 4 k x 12 bit, which is used to encode the samples in a way that the linearity of output analog digital converter (D/A) is altered. This memory is loaded with data calculated on the control computer and sent by a few lines of data, in other words, also digitally controlling the amplitude distortion.

Innovative Aspects:
The innovative architecture system minimizes the necessary operations, so the only limitation for bandwidth with which the system can work is the speed of the conversion process analog digital - digital analog and/or the reports used.